1. Field of the Invention
The present invention generally relates to metal-oxide-semiconductor (MOS) devices. More particularly, the present invention relates to MOS transistors having mesh-type gate electrodes.
2. Background of the Invention
Complimentary MOS (CMOS) technology has been gaining attention as a strong candidate for current and next generation radio-frequency (RF) applications. This is because CMOS technology is characterized by relatively low process costs, high speed performance, and easy integration for SoC. For RF applications, CMOS transistors must have a large width-to-length (W/L) ratio to obtain sufficient drive power, and the CMOS transistors must further have a low gate resistance and low parasitic capacitance to operate in higher frequencies. However, increasing the W/L ratio results in an increase in the gate resistance and a decrease in operation speed. As such, in an effort to increase the W/L ratios as well as lower gate resistance, a finger-type MOS transistor has been developed as shown in FIG. 1.
Referring to FIG. 1, the finger-type MOS transistor is characterized by a gate electrode 1 having a plurality of strip electrodes 1b extending between two connecting electrodes 1a. Source regions 2 and drain regions 3 are alternately arranged between the strip electrodes 1b. In the figure, W denotes the gate width, and L denotes the length of each strip electrode 1b positioned between the source and drain regions 2 and 3. Since adjacent pairs of strip electrodes 1b share a common drain region 3, each strip electrode 1b of the finger-type MOS structure has an effective gate width-to-length ratio of 2 W/L. As such, the finger-type MOS structure exhibits a reduced gate resistance.
The gate resistance of an MOS transistor can be further reduced by adopting a mesh-type structure as shown in FIGS. 2(a) and 2(b). Referring first to FIG. 2(b), the mesh-type MOS transistor structure is characterized by mesh-type gate 100 having a plurality of first strip electrodes 100a intersecting a plurality of second strip electrodes 100b to define an array of source/drain regions S, D within an active area 120. As shown, the first strip electrodes 100a terminate at one end at a common electrode 100c. In the figure, W denotes the gate width, and L denotes the length of each strip electrode 100a and 100b between source and drain regions. The four regions directly vertically and horizontally adjacent source region S are all drain regions D, and the four regions directly vertically and horizontally adjacent the drain regions D are all source regions S. Each unit area of the mesh-type MOS structure therefore has an effective gate width-to-length ratio of 4 W/L, but gate resistance is substantially maintained. Therefore, sufficient drive power is obtained along with a low gate resistance despite the increase in the W/L ratio.
FIG. 2(a) shows additional structural details of the mesh-type MOS transistor. In this figure, reference numbers 123 and 124 denote conductive structures which overlay the gate electrode 100 (through one or more interlayer insulating layers, not shown) and which are for electrical connection to the source and drain regions, respectively, of the active area 120. Reference numbers 140 and 160 denote contact holes for connecting the source and drain regions to the conductive structures 123 and 124, respectively.
FIG. 2(c) is a cross-sectional view of a unit area of the mesh-type MOS transistor taken along line I–I′ of FIG. 2(b). As shown, a gate oxide 101 is interposed between the gate 100 and active region 120 of the silicon substrate. Source and drain regions S and D are defined on opposite sides of the gate 100.
As suggested above, the gate resistance of the mesh-typed CMOS layout is significantly less than that of the finger-typed CMOS layout (4 W/L vs. 2 W/L) because of the number of alternate parallel paths at any given point in the mesh-typed structure. Disadvantageously, however the gate capacitance of the mesh-typed CMOS layout is larger than that of the finger-typed layout. As shown in FIG. 2(b), the vertical and horizontal stripe electrodes 100a and 100b intersect with one another to define a plurality of intersecting gate regions. Each of the intersecting gate regions creates a parasitic capacitance at the gate. When the transistor is turned on, current flows from each source region S to each drain region D through channels beneath the stripe electrodes 100a and 100b. On the other hand, current does not flow in the active area beneath the intersecting gate regions of the gate 100. Nevertheless, a thin gate oxide layer is present between the gate intersecting regions and the active area, and these regions thus contribute to presence of parasitic capacitance at the gate.
In the conventional mesh-typed CMOS layout exhibits a small gate resistance. However, the gate capacitance is relatively large, which makes it difficult to achieve a high power gain.
Also, while the gate resistance of the mesh-type CMOS transistor is relatively small, it would be desirable to even further reduce the resistive characteristics of the mesh-type gate MOS transistor.